The present invention relates to semiconductor design, and more particularly, to a semiconductor memory device for generating a data strobe reset signal for preventing ring-back of a data strobe signal, and an operation method thereof.
In general, a semiconductor memory device performs a write operation for receiving data from an external circuit such as a chip set and storing the received data, and also performs a reading operation for outputting the stored data to a chipset. Lately, data are transmitted and received with a data strobe signal for high speed data transmission. Here, the data strobe signal basically sustains high impedance when toggled with synchronized data, and sustains high impedance when the data ends. However, the data strobe signal may cause ring-back. Therefore, the data strobe signal is reset to a logical ‘low’ level by a data strobe reset signal
FIG. 1 is a block diagram illustrating a partial circuit of a semiconductor memory device for generating a data strobe reset signal according to the related art.
Referring to FIG. 1, the semiconductor memory device includes a write pulse signal generator 110, a shifter 120, a first reset signal generator 130, an output selector 140, a reset signal output unit 150, and a second reset signal generator 160.
The write pulse signal generator 110 synchronizes a write instruction WT with an internal clock signal CLKP4 and outputs a write pulse signal WTP. The write pulse signal WTP is a pulse signal that is activated when the semiconductor memory device performs a write operation. The write pulse signal WTP informs a plurality of internal circuits of a write operation time. The internal clock signal CLKP4 is a slightly delayed signal compared to an external clock signal. The internal clock signal CLKP4 is a clock signal considered with a setup-hold time of the write instruction WT. For the reference, the write instruction WT is one of internal instructions that are generated by decoding a chip select signal, a row address strobe signal, a column address strobe signal, and a write enable signal, which are external instruction signals. The internal instructions may further include a read instruction, a pre-charge instruction, and an active instruction.
The design of the write pulse signal generator 110 is similar to a circuit for processing an external instruction such as a write instruction WT to be used internally. That is, the write pulse signal WTP is a signal inputted to a plurality of internal circuits when a write operation of the semiconductor memory device is performed. Therefore, the write pulse signal generator 110 cannot be designed specifically suitable to a predetermined internal circuit. That is, the write pulse generator 110 must be designed to a proper location in consideration of all of internal circuits. So, the write pulse signal WTP is transferred to the shifter 120 and the first and second reset signal generators 130 and 160 with slight delay due to a long transmission line.
The shifter 120 generates first to third shifting signal SFT_WTP1, SFT_WTP2, and SFT_WTP4 by shifting the write pulse signal in response to an internal clock signal CLKP4 and performs a reset operation in response to a first reset signal RSTB1. That is, the first to third shifting signals SFT_WTP1, SFT_WTP2, and SFT_WTP4 are reset to a predetermined logical level value in response to the first reset signal RSTB1.
The first reset signal generator 130 generates a power up signal PWRUP and a first reset signal RSTB in response to the write pulse signal WTP. The power up signal PWRUP is a signal activated if an external power voltage has an enough voltage level in a power on state of the semiconductor memory device. The semiconductor memory device can prevent critical damage such as latchup using the power up signal PWRUP. For the reference, the power up signal PWRUP has a characteristic that a ground power voltage is sustained while the external power voltage increases to a target voltage level and the ground power voltage transits to the external power voltage if the external power voltage becomes greater than the target voltage level.
FIG. 2 is a circuit diagram illustrating a first reset signal generator 130 of FIG. 1.
Referring to FIG. 2, the first reset signal generator 130 includes a first inverter INVL for receiving and inverting a power up signal PWRUP and a first NOR gate NOR1 for generating a first reset signal RSTB1 in response to a write pulse signal WTP and an output signal of the first inverter INV1. The first reset signal generator 130 outputs a first reset signal RSTB1 by inverting the write pulse signal WTP after the power up signal PWRUP transmits because it becomes greater than the target voltage level.
Referring to FIG. 1 again, the output selector 140 selects one of the first to third shifting signals SFT_WTP1, SFT_WTP2, and SFT_WTP4 according to first to third burst length BL2, BL4, and BL8. The first burst length BL2 is activated when a burst length is 2, the second burst length BL4 is activated when the burst length is 4, and the third burst length BL8 is activated when the burst length is 8. In general, the output selector 140 selects the first shifting signal SFT_WTP1, which is obtained by shifting the write pulse signal WTP once when the burst length is 2. Also, the output selector 140 selects the second shift signal SFT_WTP2, which is obtained by shifting the write pulse signal WTP twice when the burst length is 4. The output selector 140 selects the third shifting signal WT4, which is obtained by shifting the write pulse signal WTP four times when the burst length is 8.
The reset signal output unit 150 generates a data strobe reset signal DISDSP in response to an output signal of the output selector 140 and a control clock signal DSFP2. The control clock signal DSFP2 is a signal generated in response to a falling edge of the data strobe signal (see FIG. 3). The reset signal output unit 150 performs a reset operation in response to the second reset signal RSTB2. That is, the data strobe reset signal DISDSP is reset in response to a second reset signal RSTB2.
The second reset signal generator 160 generates a second reset signal RSTB2 in response to a write pulse signal WTP. Here, the second reset signal RSTB2 is a signal obtained by inverting the write pulse signal and extending a pulse width thereof. FIG. 3 shows the second reset signal RSTB2.
Meanwhile, the data strobe signal is reset to a predetermined logical level value in response to the generated data strobe reset signal DISDSP. Finally, the ring-back of the data strobe signal is prevented.
However, a data strobe reset signal generating circuit according to the related art has below problems when the write operation is performed continuously. Hereinafter, the problem of the data strobe reset signal generating circuit will be described with reference to FIG. 3.
FIG. 3 is a timing diagram for describing timing of each signal in FIG. 1. FIG. 3 illustrates an internal clock signal CLKP4, a write pulse signal WTP, a first reset signal RSTB1, a second shifting signal SFT_WTP2, a control clock signal DSFP2, a second reset signal RSTB2, a data strobe reset signal DISDSP, an extern data strobe signal DQS inputted from an external device, and an internal data strobe signal DQS_INN internally used. For convenience, those signals will be described when the burst length is 4. That is, the output selector 140 (see FIG. 1) selects the second shifting signal SFT_WTP2 in response to the second burst length BL4. Here, the second shifting signal SFT_WTP2 is a signal obtained by shifting the write pulse signal WTP twice in response to the internal clock signal CLKP4.
Referring to FIGS. 1 and 3, a write pulse signal WTP synchronized with the internal clock signal CLKP4 is activated when a first write instruction TW1 is applied. The write pulse signal WTP is transferred to the shifter 120 and the first and second reset signal generators 130 and 160 with slight delay due to a long transmission line as shown in drawings.
Continuously, the first and second reset signals RSTB1 and RSTB2 are activated in response to the delayed write pulse signal WTP. The first reset signal RSTB1 is a signal obtained by inverting the write pulse signal WTP, and the second reset signal RSTB2 is a signal obtained by inverting the write pulse signal WTP and extending a pulse width thereof.
After releasing from reset by the first reset signal RSTB1, the shifter 120 shifts the activated write pulse signal WTP in response to an internal clock signal CLKP4, and the output selector 140 outputs the second shifting signal SFT_WTPS corresponding to the burst length 4 as shown in {circle around (1)}. Then, the second shifting signal SFT_WTPS2 activates a data strobe reset signal DISDSP corresponding to the first write instruction TW1. Meanwhile, if the second write instruction WT2 is consecutively applied, the internal data strobe is reset to a logical low as shown in {circle around (2)} although the external data strobe signal DQS is activated and applied to the semiconductor memory device.
In other words, the second shifting signal SFT_WTP2 is activated corresponding to the first write instruction TW1 as shown in {circle around (1)}, and the activate second shifting signal SFT_WTP2 activates a data strobe reset signal DISDSP so as to reset the internal strobe signal DQS_INN to a logical low as shown in {circle around (2)} although the second write instruction WT2 is applied. That is, a pulse width of the internal data strobe signal DQS_INN corresponding to the second write instruction WT2 is reduced
Meanwhile, if the internal data strobe signal DQS_INN and data cannot satisfy tDQSS with data assigned as SPEC., data cannot be inputted. Here, tDQSS defines a period of inputting data with the internal data strobe signal DQS_INN as a reference. The data must be inputted to be suitable to tDQSS with the internal data strobe signal DQS_INN as a reference.
However, a pulse width of the internal data strobe signal (DQS_INN) is reduced due to an undesired activation of the data strobe reset signal DISDSP in a circuit. It is because glitch is generated at the second shifting signal SFT_WTP2 as shown in {circle around (1)}. As described above, if the pulse width of the data strobe signal DQS_INN is reduced by glitch, the semiconductor memory device cannot properly receive data.
Such a problem becomes serious as an operation frequency of the semiconductor memory device gradually increases to a high frequency. Therefore, the semiconductor memory device cannot internally recognize data although the semiconductor memory device receives data from an external device. Such a problem decreases reliability of the semiconductor memory device.